View SI3500_8094947.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.1 10/09 copyright ? 2009 by silicon laboratories SI3500 50 v i nput dc to dc c onverter features applications description the SI3500 is a highly-integrated, hi gh-voltage (42 to 57 v) input dc-to-dc converter with integrated pwm control and power fet. the output can be adjusted for various applications in the range of 1.8 to 12 vdc. the integrated hot swap switch provides a 2-level current limit for slow charging of the input filter capacitor followed by overcurrent protection at 400 ma. the hot swap switch overcurrent protection fully protects the SI3500 from short-circuit damage as long as the inductor does not saturate. for situations where it is desirable to use a smaller inductor, it is possible to reduce the overcurrent protection with the addition of one low-cost transistor. the SI3500 can be configured to provide an isolated output voltage or a non-isolated output that is positive or negative with respect to the positive input rail. input undervoltage and overvoltage lo ckout functions are fully-integrated. a 65 v input clamp is also integrated. output voltage softstart is enabled by just one capacitor to control the output rise time at startup. ? integrated switching regulator controller with on-chip power fet ? input range 42 to 57 v ? output can be set from 1.8 to 12 v ? output power up to 10 w ? highly-integrated ic enables compact solution footprints ?? minimal external components ?? integrated transient surge suppressor ?? integrated dual current-limited hotswap switch ?? integrated switching power fet ? supports non-isolated and isolated switching topologies ? comprehensive protection circuitry ?? transient overvoltage protection ?? undervoltage lockout ?? thermal shutdown protection ?? short circuit protection ? 50% duty cycle limiting ? low-profile, 5x5 mm, 20-pin qfn ? rohs-compliant ? 3.3 v power supply generation for power over ethernet power sourcing supply, such as si3452 ? internet appliances ? network devices ordering information: see ordering guide on page page 14. pin assignments 5x5mm qfn (top view) vneg (pad) erout ssft rbias hso nc nc nc vposf nc nc nc isossft vdd 5678 9 10 1516 20 19 18 17 1 2 3 4 11 12 13 14 vneg vssa vposs vss1 swo vss2 fb SI3500
SI3500 2 rev. 1.1 functional block diagram error amplifier pwm soft start control central bias protection vpos1 vpos2 rbias vdd isossft ssft fb erout vssa hso vneg vss1 vss2 swo SI3500
SI3500 rev. 1.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schemati cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. input surge protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. dual current limit hot swap switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4. switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5. switcher startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6. switching regulator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. recommended pcb land ing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
SI3500 4 rev. 1.1 1. electrical specifications table 1. recommended operating conditions description symbol min typ max units vpos ? vneg input voltage vin 42 ? 57 v ambient operating temperature t a ?40 25 85 c note: unless otherwise noted, all voltages referenced to vneg. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typi cal values apply at nominal supply voltage and ambient temperature unless otherwise noted. table 2. absolute maximum ratings (dc) 1 type description rating unit voltage vpos ?0.3 to 60 v hso ?0.3 to 60 v vss1 or vss2 ?0.3 to 60 v swo 2 ?0.3 to 60 v current vpos 3 0 to 400 ma vdd 0 to 2 ma swo 0 to 3 a vss1, vss2, or vssa 0 to 400 ma ambient temperature storage ?65 to 150 c operating ?40 to 85 c notes: 1. unless otherwise noted, all voltages referenced to vn eg. permanent device damage may occur if the maximum ratings are exceeded. functional operation should be restricted to those conditions specified in the operational sections of this data sheet. exposure to absolute maximu m rating conditions for extended periods may adversely affect device reliability. 2. averaged over th e switching cycle. 3. vpos is equal to vpos1 and vpos2 ti ed together for test condition purposes.
SI3500 rev. 1.1 5 table 3. absolute maximum ratings (transient) 1 type description rating unit voltage vpos 2 ?0.7 to 80 v hso ?0.7 to 80 v vss1, vss2, or vssa ?0.7 to 80 v swo ?0.7 to 80 v current vpos 2 ?5 to 5 a notes: 1. unless otherwise noted, all voltages referenced to vneg. pe rmanent device damage may o ccur if the maximum ratings are exceeded. functional operation should be restricted to thos e conditions specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 2. vpos is equal to vpos1 and vpos2 tied together for test condition purposes. table 4. surge immunity ratings 1,2 type description rating unit esd (system-level) air discharge (iec 61000-4-2) ?16.5 to 16.5 kv contact discharge (iec 61000-4-2) ?8 to 8 kv esd (cdm) jedec (jesd22-c101c) ?750 to 750 v esd (hbm) jedec (jesd22-a114e) ?2 to 2 kv esd (mm) jedec (jesd22-a115a) ?150 to 150 v notes: 1. permanent device damage may occur if the maximum ratings are exceeded. func tional operation should be restricted to those conditions specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 2. care should be taken to follow layout guidelines.
SI3500 6 rev. 1.1 table 5. electrical characteristics parameter description min typ max unit current limit 1 inrush ? 140 ? ma operating 400 525 ? ma hotswap fet on-resistance + r sense 0.5 ? 1.5 ? switcher frequency ? 350 ? khz maximum switcher duty cycle isossft connected to vdd ?50?% switching fet on-resistance 0.3 ? 0.86 ? regulated feedback @ pin fb 2 dc avg. ? 1.23 ? v regulated output voltage tolerance 2 output voltage tolerance @ vout ?5 ? 5 % vdd accuracy @ 0.8 ma 42 v < vpos < 57 v 4.5 ? 5.5 v softstart charging current non-isolated ? 25 ? a isolated ? 13 ? a thermal shutdown junction temperature ? 160 ? c thermal shutdown hysteresis ? ? 25 c notes: 1. at turn-on, before the hso load capacitor is charged, the current limit is set at the inrush level. af ter the capacitor has been charged within ~1.25 v of vneg, the operating current limit is engaged. this higher current limit remains active until the uvlo lower limit has been tripped or until the hotswap switch is sufficiently current-limi ted to cause a foldback of the hso voltage. 2. applies to non-isolated applications on ly (vout on schematic in figure 1). table 6. total power dissipation description condition min typ max units power dissipation vin = 50 v, vout = 5 v, 2 a ? 0.7 ? w table 7. package thermal characteristics parameter symbol test condition typ units thermal resistance (junction to ambient) ? ja still air; assumes a minimum of nine thermal vias are connected to a 2 in 2 heat spreader plane for the package ?pad? node (vneg). 44 c/w
SI3500 rev. 1.1 7 2. typical application schematics figure 1. schematic (non-isolated 3.3 v output)* *note: this is a simplified schematic. re fer to si3452 reference design databases for complete application schematic. figure 2. schematic (isolated 3.3 v output)* *note: this is a simplified schematic. re fer to si3452 reference design databases for complete application schematic. cin SI3500 24.9 k ? vneg rbias hso 68 h cout fb cssft ssft -vout vposs vposf vss vssa erout swo ccomp -vin +vin 50v +vout 3.3 v optional hot swap damping c1 SI3500 vneg rbias hso vss1 swo c3 ssft d1 r5 r7 r6 tlv431 ps2911 t1 r2 fb vdd erout vout r1 isossft vss2 r3 c5 c4 r4 c7 vposf vposs vssa d2 d3 c8 -vin +vin 50v optional hot swap damping r8
SI3500 8 rev. 1.1 figure 3. schematic?non-isolated 3.3 v output* *note: this is a simplified schematic. re fer to si3452 reference design databases for complete application schematic. figure 4. startup waveform for current in figure 3 c1 SI3500 vneg rbias hso vss1 swo c3 ssft d1 r5 r7 r6 tlv431 ps2911 t1 r2 fb vdd erout vout r8 isossft vss2 r3 c5 c4 r4 c7 vposf vposs vssa c8 -vin +vin 50v r1 erout optional to reduce short circuit current limit connect to +vin
SI3500 rev. 1.1 9 3. functional description 3.1. input surge protection the SI3500 has a 65 v zener diode clamp on the input between vpos1 and vneg. the diode is designed to limit the input voltage to less than 80 v for surges of up to 5 a and 50 sec duration. this provides protection against hot plugging the input power supply. if the input power supply is hot plugged and there is no surge limiting resistance, there can be an overshoot of input voltage due to lead inductance. for this reason, an optional surge limiting resistor of 2 ? is recommended. this is particularly true if emc reduction capacitor is placed directly across vpos and vneg. 3.2. under voltage lockout the SI3500 incorporates an undervoltage lockout (uvlo) circuit to monitor the line voltage and determine when to activate the inte grated switching regulator. before power is applied to the switching regulator, the hotswap switch output (hso) pin is high-impedance and typically follows vpos as the input is ramped (due to the discharged switcher supply capacitor). when the input voltage rises above the uvlo turn-on threshold (42 v maximum), the SI3500 turns on the internal hotswap power mosfet. the switcher supply capacitor begins to charge up under the current limit control of the SI3500, and the hso pin transitions from vpos to vneg. the SI3500 includes hy steresis in uvlo circuits to maintain power to the lo ad until the input voltage falls below the uvlo turn-off threshold. once the input voltage falls below 30 v (minimum), the internal hotswap mosfet is turned off. 3.3. dual current limit hot swap switch the SI3500 implements dual current limits. while the hotswap mosfet is charging the switcher supply capacitor, the SI3500 main tains a lower current limit. the switching regulator is disabled until the voltage across the hotswap mosfet becomes sufficiently low, indicating the switcher supply capacitor is almost completely charged. when this threshold is reached, the switcher is activated, and the hotswap current limit is increased. this threshold also has hysteresis to prevent systemic oscillation as the switcher begins to draw current and the current limit is increased. the SI3500 stays in a high-level current limit mode until the input voltage drops below the uvlo turn-off threshold or excessive power is dissipated in the hotswap switch. this dual-lev el current limit gives low current draw from the input power supply during normal start up with the higher current only occurring during fault conditions. 3.4. switching regulator the SI3500 can be configured to provide output that is either more positive, more negative, or isolated from the positive terminal of the input power supply. the application determines the converter topology. an isolated application will requ ire a flyback transformer- based switching topology while a non-isolated application can use an inductor-based buck converter topology. in the isolated ca se, dc isolation is achieved through a transformer in the forward path and a voltage reference plus opto-isolator in the feedback path. the application circuit shown in figure 2 is an example of such a topology. the non-isolated application in figure 1 makes use of a single inductor as the energy conversion element, and the feedback signal is directly supplied into the internal er ror amplifier. the approach shown in figure 3 is for a non-isolated application where the output is more positive than the input. 3.5. switcher startup the switching regulator is disabled until the hotswap interface has charged the supply capacitor needed to filter the switching regulator's high-current transients. once the supply capacitor is charged, the hotswap controller engages the internal bias currents and supplies used by the switcher. additionally, the soft-start current begins to charge the external soft-start capacitor. the voltage developed across the soft-start capacitor serves as the error amplifier's reference in the non- isolated application. ramping this voltage slowly allows the switching regulator to bring up the regulated output voltage in a cont rolled manner. cont rolling the initial startup of the regulated voltage restrains power dissipation in the switching fet and prevents overshoot and ringing in the output supply voltage. in the isolated mode, a capacitor connected between pins isossft and vssa slowly ramps the duty cycle clamp in the pwm circuit. tie the isossft pin to vdd if not used. 3.6. switching regulator operation the switching regulator of the SI3500 is a constant- frequency, pulse-width-modulated (pwm) controller integrated with switching power fet optimized for the output power range of up to 10 w. once the hotswap interface has ensured proper turn-on of the switching regulator cont roller, the switcher is fully operational. an internal fr ee-running oscillator and internal precision voltage reference are fed into the pulse-width modulator. the output of the error amplifier (either internal for non-isolated applications or external
SI3500 10 rev. 1.1 for isolated applications) is also routed into the pwm and determines the slicing of the oscillator. the pwm controls the switch ing fet drive circuitry. a significant advantage of integrating the switching power fet onto the same monolithic ic as the switching regulator co ntroller is the ability to precisely adjust the drive strength and timing to the fet's sizable gate, resulting in high regulator efficiency. furthermore, current-limiting circuitry prevents the switching fet from sinking too much current, dissipating too much power, and becoming damaged. thermal overload protection provides a secondary level of protection. the flexibility of the SI3500's switching regulator allows the system designer to realize either the isolated or non- isolated application circuitry using a single device. in operation, the integration of the switching fet allows tighter control and more efficient operation than a general-purpose switching regulator coupled with a general-purpose external fet. 4. layout guidelines the following are general pcb layout considerations; reference designs are also available. due to the unique high-voltage and high-power design considerations, silicon labs recomme nds that the reference designs be followed closely for both bom and layout. visit the silicon labs technical support web page and register to submit a technical support request, particularly if you are not closely following the recommended reference design. care must be taken to connect the thermal pad of the SI3500 to an appropriate heat spreader. for full-power applications, a 2 square in plane with at least 9 thermal vias is recommended. this heat spreader must be electrically connected to the negative input power supply. care must also be taken in layout to avoid emi and emc. input and output filter capacitors are normally ceramic capacitors for high-frequency performance in parallel with electrolytic ca pacitors for load transient performance. the ceramic capacitors in particular should be placed so as to minimize radiation for the high-current paths of the switching regulator. the circular area of current flow with the fet on and fet off should be minimized. the direction of current flow with fet on and fet off should maintain a constant clockwise or counterclockwise rotation. for emi reduction, a 4 layer design with inner layers connected to the positive input and vss (for isolated applications) or vout (for non-isolated applications) is recommended. the high-current paths should not flow through these shield planes. connection of the dc-to-dc converter high-current paths to the shield plane should be at a single point. refer to the si3452 reference design databases for additional layout guideline details.
SI3500 rev. 1.1 11 5. pin descriptions table 8. SI3500 pin descriptions (top view) pin# name description 1 erout error-amplifier output and pwm input; direct ly connected to opto-coupler in isolated or boost applications. 2 ssft soft-start output pin ramps voltage across exte rnal soft-start capacitor to allow switcher to ramp output slowly. 3 vdd 5 v supply rail for switcher; provides drive for opto-coupler. 4 isossft isolated mode soft start enable i nput. tie to vdd for non-isolated applications. connect a 0.1 f capacitor between this pin and vssa for isolated applications. 5 nc do not connect (float). 6 rbias a 25.5 k ? resistor connected from this to vpos sets up the bias currents of the SI3500. 7 hso hotswap switch output; connects to vneg through hotswap switch. 8 nc do not connect (float). 9, pad vneg rectified high-voltage supply, negative rail. must be connected to thermal pad node (vneg) on package bottom. this thermal pa d must be connected to vneg (pin #9) as well as a 2 in 2 heat spreader plane using a minimum of nine thermal vias. 10 nc do not connect (float). 11 nc do not connect (float). 12 vpos1 high-voltage supply, positive rail (force node) 13 nc do not connect (float). 14 nc do not connect (float). 15 vssa analog ground. vneg (pad) erout ssft rbias hso nc nc nc vposf nc nc nc isossft vdd 5678 9 10 1516 20 19 18 17 1 2 3 4 11 12 13 14 vneg vssa vposs vss1 swo vss2 fb
SI3500 12 rev. 1.1 16 vpos2 high-voltage supply, positive rail sense node. 17 vss1 negative supply rail for swit cher; externally tied to hso. 18 swo switching transistor outpu t; drain of switching n-fet. 19 vss2 negative supply rail for swit cher; externally tied to hso. 20 fb regulated feedback input in non-isolated application. table 8. SI3500 pin descriptions (top view) (continued)
SI3500 rev. 1.1 13 6. package outline figure 5 illustrates the package details for the SI3500. table 9 lis ts the values for the di mensions shown in the illustration. figure 5. 20-lead quad flat no-lead package (qfn) table 9. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.25 0.30 0.35 d 5.00 bsc. d2 2.60 2.70 2.80 e 0.80 bsc. e 5.00 bsc. e2 2.60 2.70 2.80 l 0.50 0.55 0.60 l1 0.00 ? 0.10 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec soli d state outline mo-220, variation vhhb-1.
SI3500 14 rev. 1.1 7. recommended pc b landing pattern figure 6. pcb land pattern
SI3500 rev. 1.1 15 table 10. pcb land pattern dimensions symbol min nom max p1 2.70 2.75 2.80 p2 2.70 2.75 2.80 x1 0.25 0.30 0.35 y1 0.90 0.95 1.00 c1 4.70 c2 4.70 e0 . 8 0 general: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is bas ed on the ipc-7351 guidelines. solder mask design: 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 5. a stainless steel, laser-cut and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 2x2 array of 1.2 mm square openings on 1.4 mm pitch should be used for the center ground pad. card assembly: 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
SI3500 16 rev. 1.1 8. ordering guide part number * package temp range recommended maximum output power SI3500-a-gm 20-pin qfn, rohs compliant ?40 to 85 c < 10 w *note: add an ?r? at the end of the part number to denote tape and reel option.
SI3500 rev. 1.1 17 d ocument c hange l ist revision 0.1 to revision 1.0 ? updated revision number to 1.0 to reflect production status. ? updated table 4 on page 5. revision 1.0 to revision 1.1 ? editorial changes in "4. layout guidelines" on page 10.
SI3500 18 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

▲Up To Search▲

Price & Availability of SI3500

	To Download SI3500 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .